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In full-duplex communication systems such as W-CDMA, a receiver’s tolerance to unwanted transmit signals, including a co-located transmitter, is significantly important since transmission and reception occur simultaneously. Since transmit signals can be as little as 30 MHz away in frequency from the receive signal, surface acoustic wave (SAW) filters are typically employed to reject such close-in interferers. The receiver’s low noise amplifier (LNA) must accommodate all signal levels delivered at the SAW filter output. In this article, a highly signal-tolerant LNA is designed, with a worst-case 1 dB compression point (P1dB) of -11 dBm, a gain (S₂₁) of over 17 dB and a noise figure (NF) close to 2.6 dB, for implementation in 0.35 mm, 4-metal CMOS technology.

A conventional direct conversion receiver is described in Figure 1, in which a common antenna is used for both transmission and reception of the radio signal. The commonpath to the antenna is established by the duplex filter and further filtering is provided by individual transmit and receive filters as required. In a full-duplex W-CDMA system, the maximum power amplifier (PA) output power is 29 dBm, which will find its way to the receiver via the duplexer, as shown in the Figure.

From W-CDMA 3GPP specifications,^1,2 the maximum signal at the input to the receiver is -25 dBm at the low gain setting and -43 dBm at the high gain setting. An LNA filter therefore has to attenuate the transmitter signal by at least 43 + 29 = 72 dB, when operating the LNA at the prescribed -43 dBm, in order to prevent the LNA from being compressed by the transmitter signal.

A filter that produces 72 dB of attenuation of the transmission signal will inevitably require a considerable amount of poles, which in turn would imply that the wanted frequency band itself will be subjected to losses due to this filtering process. By improving the linearity of the receiver path and in particular the LNA, it is possible to implement a low-loss filter with fewer poles. Fewer poles in the receive path inevitably means a filter with reduced signal loss at the wanted receiver frequency, thereby resulting in an increase in sensitivity of the receiver. By considering a highly linear LNA, with an input P_1dB of -14 dBm or better, the SAW filter in the receive path can be removed, thereby substantially reducing receiver path losses and reducing component count and cost of the receiver (see Table 1).

The Method of Achieving the Increased Compression Point

In the power amplifier world, highly linear amplifiers are designed such that the transistor is biased either at the class B or class AB bias points. In this work, the same technique is employed to achieve a highly linear LNA, by biasing the transistor at the class AB bias point. This technique, however, lowers the transconductance (g_m) value, reducing the gain of the transistor and improving its dynamic range. The design is structured in two stages: A first-stage cascode amplifier, biased to a point just above the threshold voltage, followed by a second-stage PMOS amplifier. As illustrated in Figure 2, the LNA consists of an input cascode section and a second-stage drain follower. The cascode section consists of two NMOS devices M1 and M2 and an LC parallel resonant circuit consisting of L2 and C1.