To address the space, cost and power-consumption constraints of mobile portable devices from cell phones to PDAs and laptops, the trend in RFIC design is to combine the analog baseband (BB) and processor interface into a single chip solution (see Figure 1). With new products experiencing narrow market-windows and shorter product life cycles, wireless applications are increasingly faced with the need to achieve “First Pass Functional Silicon.” Silicon re-spins that are most often due to functional errors on average cost $1 M for 90 nm and below.

Meanwhile, system demands on RFIC functionality, as multi-band and multi-mode operations, for example, further complicate this objective. In order to increase RFIC “functionality and features” while ensuring greater first-pass success, design organizations are adding new design skills, software tools and design data structures to their existing flows. In this article, the author discusses his first hand experience working with design organizations as they face the challenges of developing the models, simulation capability and automation that will accurately verify the behavior of a device operating across the RF to digital domains.